搜索资源列表
i2_cmaster
- verilog HDL i2c主机代码-verilog HDL i2c host code
VERILOG.HDL
- Verilog 硬件描述语言. 很好的学习HDL语言的书籍资料.-Verilog HDL , a very good book for learning Verilog.
RAM_Examples
- Verilog hdl code for representing ram and rom "memory" using many methods
verilog
- Verilog HDL程序设计教程常用verilog模块，特别好的学习资料-" Verilog HDL Programming Guide" verilog modules used, in particular, good learning materials
traffic
- 一个很好的交通灯控制的Verilog HDL实现方式，包括LED显示部分。-A good control of traffic lights to achieve the Verilog HDL, including the LED display.
VerilogHDL
- 入门级经典《Verilog HDL Synthesis A Practical Primer》中英文版，绝对的好书！！！ -classical book Verilog HDL Synthesis A Practical Primer
state
- verilog HDL下有限状态机（FSM），麻雀虽小，但五脏俱全！值得一看-under the verilog HDL Finite State Machine (FSM), the sparrow may be small, but is a fully-equipped! Worth a visit! !
verilog_all
- Verilog HDL 详细教程，很适合初学者使用。-Verilog HDL detailed tutorial, it is suitable for beginners to use.
verilog
- Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。 Verilog HDL 语言具有下述描述能力：设计的行为特性、设计的数据流特性、设计的结构组成以及包含响应监控和设计验证方面的时延和波形产生机制。所有这些都使用同一种建模语言。此外，Verilog HDL语言提供了编程语言接口，通过该接口可以在模拟、验证期间
PWM_VerilogHDL
- altera公司网站上的详细的PWM设计的Verilog hdl源程序，大多数都采用这个-altera company' s Web site the detailed design of the PWM source Verilog hdl, most have adopted this
IIC_Verilog
- FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface
LCD
- lcd verilog hdl 源码 可以直接使用，适用modelsim-lcd verilog HDL source
FPGA
- VHDL、Verilog HDL语言，是华为公司的技术指导书，希望对你有所帮助-VHDL、Verilog HDL
Verilog_Digital_Design_Synthesis
- Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996
clock
- verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
usartverilogydm
- verilog hdl在FPGA设计中广泛应用，好的程序代码是学习verilog的好帮手-verilog hdl widely used in the FPGA design, a good code is a good helper to learn verilog
clock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
cpu_16bit
- design cpu 16 bits by verilog HDL.
Processor_alu
- this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
SDRAMverilog
- SDRAM 驱动，Verilog HDL源码-SDRAM-driven, Verilog HDL source code